1. Field of the Invention
This invention relates generally to the structure and fabrication process of power MOSFET transistors. More particularly, this invention relates to a novel and improved MOSFET termination layout design and core cell configuration in order to increase the breakdown voltage in the termination area and to improve the device ruggedness by eliminating incidental turning-on of the parasitic bipolar transistors whereby the damages caused by snapback voltage may be prevented.
2. Description of the Prior Art
The concern of device damages caused by early breakdown, particularly, breakdown in the termination area for a power MOSFET transistor with smaller cells, often becomes a technical limitation faced by device designers. The maximum blocking voltage and the conditions leading to a breakdown for a power MOSFET are dependent upon the spacing of the cells in the active core cell area and the configuration of the device termination. For the power MOSFET with small transistor cells, the depletion layer curvature is relatively larger at the edge junction when the MOSFET is under reverse bias, and the breakdown most likely occurs at the termination areas near the edge of the device. When an avalanche breakdown occurs in the termination area, large number of free electrons and holes are generated. For a N-channel device, the free electrons flows down-wardly to the drain electrode while the holes are influenced by the negative voltage of the source electrodes to migrate laterally toward the core cell area. Before these holes are finally "picked up" by the source electrodes, due to the lateral migration of large number of holes through the N.sup.+ source regions underneath the source electrodes, the parasitic bipolar transistor of the cells may be incidentally turned on. A snapback voltage caused by the turning-on of the parasitic bipolar may often cause a permanent damage to the MOSFET cells.
FIG. 1 is a partial top view of the MOSFET device 10 with the core cell area 40 and the termination area 50. There are a plurality of cells each includes source 30 surrounded by p-body 25 and the cells are arranged in a square-on-square configuration. In the termination area, the polysilicon gates are extended as "poly-fingers" 72 from the core cell area 40 outwardly to the termination area 50 with a gate runner 76 connected to these poly fingers 72 with a plurality of gate contacts, i.e., poly contact 70 form thereon. With such a layout, suppose that the width of the poly finger 72 is approximately X and the width of the gate runner 76 is Y, and X is approximately equivalent to Y. A breakdown is most likely to occur at the center of the block formed by the intersection of the gate runner 76 and the poly finger 72. The breakdown is caused by the extra length of the polysilicon Z, i.e., the diagonal distance, which has a length of: ##EQU1## Due to the longer length of poly in this diagonal direction, a breakdown is most likely to occur in the center portion of the intersecting square block formed by the gate runner 76 and the poly finger 72. This weak point of breaking down is caused by a longer distance of separation between the underneath p-body regions. Such longer distance of separations, i.e., a separation of Z, requires higher voltage before the depletion edge under the gate in these regions are be merged to form a shield for preventing a breakdown. The termination layout with the gate runner 76 to connect each poly fingers 72 thus generated breakdown weak points. An early breakdown in this configuration imposes more constraints to device design and performance limitations in addition to the concerns that device damages may occur caused by a snapback phenomena due to incidental turning-on of the parasitic bipolar transistor resulting from breakdown in the termination area.
FIGS. 2A and 2B shows a cross-sectional views along the lines of X--X' and Y--Y' in FIG. 1 respectively for the conventional N-channel MOSFET device 10. The MOSFET device 10 is supported on a n.sup.+ substrate 15 with a n.sup.- doped epitaxial drain region 20 formed thereon. A plurality of p-body regions 25 and n.sup.+ source regions 30 are formed on top of the drain region 20 as shown. The MOSFET device 10 is divided into a core cell area 40 and a termination area 50. A plurality of cells which include the p-body 25, the source regions 30, and a poly gate 35 are formed in the core cell area 40. As shown in FIG. 1, the source electrode (S) 60 is formed in the core cell area 40 while the gate runner (G) 70, the field plate (FP) 80, and the equal ring (EQR) 90 are formed in the termination area 50.
For a 30V rating device, when a breakdown occur at a breakdown voltage, e.g., a voltage between 36 to 40 volts, a large number of free electrons and holes are generated. For a high cell density MOSFET device with a high drain voltage, the breakdown is likely to occur in the termination area 50, e.g., at point 95 as that shown in FIGS. 2A and 2B. At the time of breakdown, for a N-channel MOSFET, the free electrons generated will flow down to the drain via the epi-layer 20 and the substrate 15. In the meantime, a large number of holes each carrying positive charge will migrate laterally moving toward the core cell area 40 under the influence of the source voltage applied through the source electrode 60 as that shown by the dotted lines 98. As these holes travel underneath the n.sup.+ source region 30 via the p-body 25, a parasitic bipolar of near the pn-junction may be incidentally turned on. A bipolar snapback voltage may cause permanent damages to the MOSFET device 10. A break-down in the termination area 50 thus becomes a design limit for the MOSFET device. More stringent restrictions on the design limits and MOSFET performance characteristics are imposed due to this breakdown concern.
It should be noted that, in FIG. 2B along the line Y--Y', where a contact for the field plate 80 is formed in the termination area. A very small portion of holes, i.e., holes 99 as shown, may be picked up by this small contact window through a p+ region 25'. However, since the purpose of this metal layer is for connecting the poly field plate, via a cross-over near the gate pad region, to a source electrode at a ground voltage, the effect of charge pickup is insignificant The conventional MOSFET structure, even with the field plate contact distributed in the termination area, is not sufficient to prevent the MOSFET damages which may be caused by incidental turning on of the parasitic bipolar as the result of large inflow of holes due to a breakdown in the termination area.
Therefore, there is still a need in the art of power device fabrication, particularly for MOSFET design and fabrication, to provide an improved device layout and fabrication process that would resolve these difficulties.